37.12.6 Host Interrupt Enable Register Clear
| Name: | INTENCLR |
| Offset: | 0x14 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DDISC | DCONN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RAMACER | UPRSM | DNRSM | WAKEUP | RST | HSOF | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 9 – DDISC Device Disconnection Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Disconnection interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Device Disconnection interrupt is disabled. |
| 1 | The Device Disconnection interrupt is enabled and an interrupt request will be generated when the Device Disconnection interrupt Flag is set. |
Bit 8 – DCONN Device Connection Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Connection interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Device Connection interrupt is disabled. |
| 1 | The Device Connection interrupt is enabled and an interrupt request will be generated when the Device Connection interrupt Flag is set. |
Bit 7 – RAMACER RAM Access Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The RAM Access interrupt is disabled. |
| 1 | The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access interrupt Flag is set. |
Bit 6 – UPRSM Upstream Resume from Device Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Upstream Resume interrupt is disabled. |
| 1 | The Upstream Resume interrupt is enabled and an interrupt request will be generated when the Upstream Resume interrupt Flag is set. |
Bit 5 – DNRSM Down Resume Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Down Resume interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Down Resume interrupt is disabled. |
| 1 | The Down Resume interrupt is enabled and an interrupt request will be generated when the Down Resume interrupt Flag is set. |
Bit 4 – WAKEUP Wake Up Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Wake Up interrupt is disabled. |
| 1 | The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up interrupt Flag is set. |
Bit 3 – RST BUS Reset Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Bus Reset interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Bus Reset interrupt is disabled. |
| 1 | The Bus Reset interrupt is enabled and an interrupt request will be generated when the Bus Reset interrupt Flag is set. |
Bit 2 – HSOF Host Start-of-Frame Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Host Start-of-Frame interrupt Enable bit and disable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Host Start-of-Frame interrupt is disabled. |
| 1 | The Host Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Host Start-of-Frame interrupt Flag is set. |