37.12.4 Host Frame Number
| Name: | FNUM |
| Offset: | 0x10 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FNUM[10:5] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FNUM[4:0] | MFNUM[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 13:3 – FNUM[10:0] Frame Number
These bits contains the current SOF number.
These bits can be written by software to initialize a new frame number value. In this case, at the next SOF, the FNUM field takes its new value and the MFNUM bits are cleared.
As the FNUM register lies across two consecutive byte addresses, writing byte-wise (8-bits) to the FNUM register may produce incorrect frame number generation. It is recommended to write FNUM register word-wise (32-bits) or half-word-wise (16-bits).
Bits 2:0 – MFNUM[2:0] Micro Frame Number
These bits are tied to zero when operating in full-speed mode.
These bits contains the current Micro Frame number (can vary from 0 to 7) updated every 125 us.