45.7.9 Debug Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | DBGCTRL |
| Offset: | 0x0F |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DBGRUN | |||||||||
| Access | RW | ||||||||
| Reset | 0 |
Bit 0 – DBGRUN Debug Run Mode
This bit is not affected by software reset and should not be changed by software while the PDEC module is enabled.
| Value | Description |
|---|---|
| 0 | The PDEC module is halted when the device is halted in debug mode. |
| 1 | The PDEC module continues normal operation when the device is halted in debug mode. |