45.7.11 Prescaler Value
Note: This register is write-synchronized: SYNCBUSY.PRESC must be checked to ensure the
PRESC register synchronization is complete.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PRESC |
| Offset: | 0x14 |
| Reset: | 0x00 |
| Property: | Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRESC[3:0] | |||||||||
| Access | RW | RW | RW | RW | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 3:0 – PRESC[3:0] Prescaler Value
These bits select the GCLK prescaler factor.
| Value | Name | Description |
|---|---|---|
| 0 | DIV1 | No division |
| 1 | DIV2 | Divide by 2 |
| 2 | DIV4 | Divide by 4 |
| 3 | DIV8 | Divide by 8 |
| 4 | DIV16 | Divide by 16 |
| 5 | DIV32 | Divide by 32 |
| 6 | DIV64 | Divide by 64 |
| 7 | DIV128 | Divide by 128 |
| 8 | DIV256 | Divide by 256 |
| 9 | DIV512 | Divide by 512 |
| 10 | DIV1024 | Divide by 1024 |