45.7.10 Synchronization Status

Table 45-11. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Bits 7, 8 – CC Compare Channel x Synchronization Busy

This bit is cleared when the synchronization of Compare Channel x (CCx) register between the clock domains is complete.

This bit is set when the synchronization of Compare Channel x (CCx) register between clock domains is started.

This bit is cleared when the synchronization of Count register between the clock domains is complete.

This bit is set when the synchronization of Count register between clock domains is started.

This bit is cleared when the synchronization of Filter register between the clock domains is complete.

This bit is set when the synchronization of Filter register between clock domains is started.

This bit is always read '0' when COUNTER operation mode is selected.

This bit is cleared when the synchronization of Prescaler register between the clock domains is complete.

This bit is set when the synchronization of Prescaler register between clock domains is started.

This bit is cleared when the synchronization of Status register between the clock domains is complete.

This bit is set when the synchronization of Status register between clock domains is started.

This bit is cleared when the synchronization of Control B register between the clock domains is complete.

This bit is set when the synchronization of Control B register between clock domains is started.

This bit is cleared when the synchronization of Enable register bit between the clock domains is complete.

This bit is set when the synchronization of Enable register bit between clock domains is started.

This bit is cleared when the synchronization of Software Reset register bit between the clock domains is complete.

This bit is set when the synchronization of Software Reset register bit between clock domains is started.