45.7.12 Filter Value
Note: This register is write-synchronized: SYNCBUSY.FILTER must be checked to ensure the
FILTER register synchronization is complete.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | FILTER |
| Offset: | 0x15 |
| Reset: | 0x00 |
| Property: | Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FILTER[7:0] | |||||||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – FILTER[7:0] Filter Value
These bits select the PDEC inputs filter length. The input signal minimum duration will be (FILTER+1)*tGCLK_PDEC.
These bits have no effect when COUNTER operation mode is selected.