45.7.8 Status
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STATUS |
| Offset: | 0x0C |
| Reset: | 0x0040 |
| Property: | Read-Synchronized, Write-Synchronized |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CCBUFV1 | CCBUFV0 | FILTERBUFV | PRESCBUFV | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIR | STOP | HERR | WINERR | MPERR | IDXERR | QERR | |||
| Access | R | R | RW | RW | RW | RW | RW | ||
| Reset | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
Bits 12, 13 – CCBUFVx Compare Channel x Buffer Valid [x = 1..0]
The bit is set when a new value is written to the corresponding CCBUF register.
The bit is cleared by writing a '1' to the corresponding location or automatically cleared on an UPDATE condition.
Bit 9 – FILTERBUFV Filter Buffer Valid
This bit is set when a new value is written to the PRESCALERBUF register.
The bit is cleared by writing a '1' to the corresponding location or automatically cleared on an UPDATE condition.
This bit is always read '0' when COUNTER operation mode is selected.
Bit 8 – PRESCBUFV Prescaler Buffer Valid
This bit is set when a new value is written to the PRESC register.
The bit is cleared by writing a '1' to the corresponding location or automatically cleared on an UPDATE condition.
Bit 7 – DIR Direction Status Flag
This bit reflects the HALL/QDEC direction.
in COUNTER mode, this bits is always read '0'.
| Value | Description |
|---|---|
| 0 | Clockwise direction. |
| 1 | Counter-clockwise direction. |
Bit 6 – STOP Stop
This bit reflects the HALL/QDEC decoding status.
In COUNTER mode, this bits is always read '0'.
| Value | Description |
|---|---|
| 0 | PDEC/HALL decoding is running. |
| 1 | PDEC/HALL decoding is stopped. |
Bit 5 – HERR Hall Error Flag
This flag is set when an invalid HALL code is detected.
The flag is cleared by writing a '1' to this bit location. After write to the STATUS register, ensure the SYNCBUSY.STATUS is '0' before reading.
Outside of HALL mode, this bits is always read '0'.
Bit 4 – WINERR Window Error Flag
This flag is set when the counter is outside the window monitor.
The flag is cleared by writing a '1' to this bit location. After write to the STATUS register, ensure the SYNCBUSY.STATUS is '0' before reading.
Outside of HALL mode, this bits is always read '0'.
Bit 2 – MPERR Missing Pulse Error flag
This flag is set when a missing pulse error condition is detected.
The flag is cleared by writing a '1' to this bit location. After write to the STATUS register, ensure the SYNCBUSY.STATUS is '0' before reading.
Outside of QDEC mode, this bits is always read '0'.
Bit 1 – IDXERR Index Error Flag
This flag is set when an index error condition is detected.
The flag is cleared by writing a '1' to this bit location. After write to the STATUS register, ensure the SYNCBUSY.STATUS is '0' before reading.
Outside of QDEC mode, this bits is always read '0'.
Bit 0 – QERR Quadrature Error Flag
This flag is set when an invalid QDEC transition is detected.
The flag is cleared by writing a '1' to this bit location. After write to the STATUS register, ensure the SYNCBUSY.STATUS is '0' before reading.
Outside of QDEC mode, this bits is always read '0'.