48.6.2 Interrupt Enable Clear
Note:
- Access to this register is limited to 32-bit width. Byte level access is not allowed.
- Reserved bits must always be written as ‘0’.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTENCLR |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DRP | ERR | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – DRP Data Remanence Prevention Complete Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Data Remanence Prevention Complete Interrupt Enable bit, which disables the data remanence prevention complete interrupt. Reading this bit provides the following information.
| Value | Description |
|---|---|
| 0 | Data remanence prevention complete interrupt is disabled. |
| 1 | Data remanence prevention complete interrupt is enabled. |
Bit 0 – ERR TRAM Read Error Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the TRAM Read Error Interrupt Enable bit, which disables the TRAM read error interrupt. Reading this bit provides the following information.
| Value | Description |
|---|---|
| 0 | TRAM read error interrupt is disabled. |
| 1 | TRAM read error interrupt is enabled. |