48.6.8 RAM
Note: Access to this register is limited to 32-bit width. Byte level access is not
allowed.
Table 48-8. Register Bit Attribute
Legend
| Symbol |
Description |
Symbol |
Description |
Symbol |
Description |
| R |
Readable bit |
HC |
Cleared by Hardware |
(Grey cell) |
Unimplemented |
| W |
Writable bit |
HS |
Set by Hardware |
X |
Bit is unknown at Reset |
| K |
Write to clear |
S |
Software settable bit |
— |
— |
| Name: | RAM |
| Offset: | 0x1000 + n*0x04 [n=0..2047] |
| Reset: | 0x00000000 |
| Property: | - |
Access to the
Security RAM is only permitted when CTRLA.ENABLE bit (CTRLA
<1>).
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | DATA[31:24] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | DATA[23:16] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | DATA[15:8] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | DATA[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – DATA[31:0] Security RAM
Data
