Introduction

This document describes the Microchip JESD204B stand-alone interface design and how to run the demo on a PolarFire Evaluation kit.

The main components of the demo design are as follows:

  • CoreJESD204BTX and CoreJESD204BRX IP cores implement the transmitter and receiver interfaces of the JESD204B standard. These IP cores are easy to integrate with the JESD204B- based data converters to develop high-bandwidth applications such as wireless infrastructure transceivers, software-defined radios, medical imaging systems, and radar and secure communications. They support link widths from x1 to x8, and link rates from 250 Mbps to 12.5 Gbps per lane using subclass 0, 1, and 2.
  • PolarFire transceiver interface can handle data rates ranging from 250 Mbps to 12.5 Gbps. It integrates several functional blocks to support multiple high-speed serial protocols within the FPGA.

The design operates in the loopback mode by sending the CoreJESD204BTX data to the CoreJESD204BRX IP core through one or more transceiver lanes, which are looped back on the board. A user-friendly GUI is provided for selecting the input data and error injection, and for monitoring the JESD204B link status.

For Evaluation kit, two designs are provided as follows:

  • SMA-based loopback design that runs at 6.25 Gbps lane rate (with single XCVR lane for TX and RX).
  • PCB-based loopback design that runs at 5 Gbps lane rate (with two XCVR lanes, where one lane is for TX and the other for RX).

For more information about the JESD204B interface design implementation, and all the necessary blocks and IP cores instantiated in Libero SoC, see Demo Design.

The JESD204B design can be programmed using any of the following options: