4 Simulating the PolarFire JESD204B Design

Before you begin:

  1. Start Libero SoC and select Project -> Tool Profiles.
  2. In the Tool Profiles window, select Synthesis and Simulation on the Tools panes and select the latest active installation directory paths for these two tools.

For Simulation, browse the design files folder, create Libero Project using provided TCL scripts, and click Simulate as shown in Figure 4-1. See Appendix B: Running the Tcl Script.

A testbench is provided to simulate the JESD204B PRBS pattern and waveform selection. Figure 4-2 shows the interaction between testbench and the design.

Figure 4-1. Testbench and JESD204B Demo Design Interaction

The testbench generates the test selection for the PRBS input (PRBS7, PRBS15, PRBS23, and PRBS31) and waveform input (sine wave, sawtooth wave, triangle wave, and square wave). It also monitors the JESD204B output status signals (SYNC_N, ALIGNED, and CGS_ERR) for the verification of JESD204B phases, and PRBS checker output status signals O_BAD and O_ERROR[4:0].

The following table lists the simulation signals.

Table 4-1. Simulation Signals
SignalDescription
Input Signals
P_W_SELInput to select the PRBS pattern or waveform
WAVE_SEL[1:0]Input to select the type of waveform
PRBS_SEL[1:0]Input to select the type of PRBS pattern
ERR_ENInput to enable error in the PRBS pattern
NSYSRESETActive low reset signal
SYSCLK156.25 MHz generated clock for external loopback design.

125 MHz generated clock for internal loopback design.

Output Signals
TB_DATA_OUTOutput data from CoreJESD204BRX
TB_RX_SOMFSOMF_0[3:0] signal received from the CoreJESD204BRX block
TB_RX_SOFSOF_0[3:0] signal received from the CoreJESD204BRX block
TB_SYNC_NSYNC_N signal, which indicates the link status
TB_ALIGNEDALIGNED signal, which indicates that all transceiver lanes are aligned
TB_LINK_CD_ERRLINK_CD_ERR[0] signal, which indicates a link configuration data mismatch error
TB_UCC_ERRUCC_ERR[0] signal, which indicates an unexpected control character error
TB_NIT_ERRNIT_ERR[3:0] signal, which indicates the “not in table” error. This signal is controlled by LANE0_RX_CODE_VIOLATION[3:0]
TB_DISP_ERRDISP_ERR[3:0] signal which indicates the disparity error. This signal is controlled by LANE0_RX_DISPARITY_VIOLATION[3:0]
TB_CGS_ERRCGS_ERR signal, which indicates the code group synchronization error. This signal is controlled by the CGS_ERR[0] signal.
TB_RX_READYLANE0_RX_READY signal received from the transceiver block
TB_0_BADError flag
TB_O_ERROR[4:0]Number of errors occurred during PRBS check

To run the simulation, go to Stimulus Hierarchy and verify if PF_JESD204B_SA_TOP_TB_8b file is set as active stimulus. If not set, right-click on the file and select Set as active stimulus.

In the Design Flow tab, under Verify Pre-Synthesized Design, double click Simulate to simulate the design. The Simulate option is highlighted in Figure 4-2.
Figure 4-2. Simulating the Design

When the simulation is initiated, ModelSim compiles all the design source files, runs the simulation, and configures the waveform viewer to show the simulation signals.