5 Clocking Structure

For the Evaluation Kit design, the on-board 156.25 MHz crystal oscillator (for the SMA loopback design) and the 125 MHz crystal oscillator (for the PCB loopback design) drive the XCVR reference clock. This clock provides the clock to the TX_PLL and PF_XCVR_0 blocks. The FAB_REF_CLK of the XCVR_REF_CLK block drives reset_syn, the read clock of TPSRAM_C0 and TPSRAM_C1, along with the UART block. The LANE0_TX_CLK_R of the PF_XCVR_0 block drives the ERR_GEN, CoreJESD204BTX, and DATA_GENERATOR blocks. Also, the LANE0_RX_CLK_R of the PF_XCVR_0 block drives the LED_DEBUG, PRBS_CHECKER, CoreJESD204BRX, and the write clock of TPSRAM_C0 and TPSRAM_C1 blocks.

An on-chip RC oscillator (PF_OSC) drive the enhanced receiver management logic of the transceiver.

Important: If there is any change in the data-rate or XCVR reference clock of the transceiver; reconfigure COREUART.
Figure 5-1. Clocking Structure

For the JESD204B design, LANE0_TX_CLK_R and LANE0_TX_CLK_R clocks are set to Regional (Deterministic) in the XCVR configurator.

The following table lists all of the clocks used in the design, their source, frequency, and purpose.

Table 5-1. Clocks
Clock NameSourceFrequencyPurpose
FAB_REF_CLOCKReference clock from the oscillator156.25 MHz/125 MHz1Clock for the fabric logic that is, reset synchronizer, read clock of TPSRAM blocks, UART block.
REF_CLKReference clock from the oscillator156.25 MHz/125 MHz1CDR reference clock for the transceiver
LANE0_TX/RX_CLK_RTransceiver generated TX/RX clock156.25 MHz/125 MHz1Clock for the transmit and receive modules in the fabric
CTRL_CLKOn-chip RC oscillator (PF_OSC)40 MHz (through clock divider PF_CLK_DIV_C0)Clock for the enhanced receiver management logic
(1) For SMA and PCB loopback designs (Evaluation kit), the frequency is 156.25 MHz and 125 MHz respectively.