11 Appendix 3: References
(Ask a Question)This section lists the documents that provide more information about the JESD204B standard and IP cores used in the demo design.
- For more information about the JESD204B interface standard, see JEDEC website.
- For more information about PolarFire transceiver blocks, PF_TX_PLL, and PF_XCVR_REF_CLK, see PolarFire FPGA and PolarFire SoC FPGA Transceiver User Guide.
- For more information about PF_TPSRAM (Two-Port Large SRAM), see PolarFire FPGA and PolarFire SoC FPGA Fabric User Guide.
- For more information about CoreJESD204BTX, see CoreJESD204BTX Handbook from Libero SoC catalog.
- For more information about CoreJESD204BRX, see CoreJESD204BRX Handbook from Libero SoC catalog.
- For more information about Libero, ModelSim, and Synplify, see Libero SoC web page.
- For more information about PolarFire FPGA Evaluation Kit, see UG0747: PolarFire FPGA Evaluation Kit User Guide.