2.3.2.3 SerDes PLL

  • Plane routing for SERDES_1_L01_VDDAPLL and SERDES_1_L01_REFRET is shown in the following figure.
  • SERDES_1_L01_VDDAPLL and SERDES_1_L01_REFRET should not be routed as traces. A small trace width causes poor noise performance due to the high inductive behavior of the trace. Even though the current requirement is low, these supply traces should be routed as small planes, as shown in the following figure.

  • The connections of 1.2 kΩ resistor and SERDES_1_L01_REXT of SmartFusion2/IGLOO2 must not be routed as a thick plane. It must be routed as a signal trace to meet minimum capacitance requirement of the SERDES_1_L01_REXT pin. The length of the trace should be short. The following figure shows the sample layout.

  • Same layout guidelines should be followed for the remaining SerDes PLL power supplies.

    Figure 2-9. Layout of SERDES_1_L01_VDDAPLL and SERDES_1_L01_REFRET