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SmartFusion 2 and IGLOO 2 FPGA Board and Layout Design Guidelines
SmartFusion 2 and IGLOO 2 FPGA Board and Layout Design Guidelines
  1. Home
  2. 2 Layout Guidelines for SmartFusion 2 and IGLOO 2-Based Board Design
  3. 2.8 High-Speed Serial Link (SerDes)

  • Introduction
  • 1 Design Considerations
  • 2 Layout Guidelines for SmartFusion 2 and IGLOO 2-Based Board Design
    • 2.1 Power Supply
    • 2.2 Core Supply (VDD)
    • 2.3 SerDes
    • 2.4 DDR
    • 2.5 PLL
    • 2.6 I/O Power Supply
    • 2.7 Programming Power Supply (VPP or VCCENVM)
    • 2.8 High-Speed Serial Link (SerDes)
      • 2.8.1 Layout Considerations
      • 2.8.2 Via
      • 2.8.3 DC Blocking Capacitors
      • 2.8.4 Connectors
    • 2.9 Considerations for Simulation
    • 2.10 DDR3 Layout Guidelines
    • 2.11 References
  • 3 PCB Inspection Guidelines
  • 4 Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs
  • 5 Board Design and Layout Checklist
  • 6 Appendix A: Special Layout Guidelines—Crystal Oscillator
  • 7 Appendix B: Stack-Up
  • 8 Appendix C: Dielectric Material
  • 9 Appendix D: Power Integrity Simulation Topology
  • 10 Appendix E: X-Ray Inspection
  • 11 Revision History
  • Microchip FPGA Support
  • Microchip Information

2.8 High-Speed Serial Link (SerDes)

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The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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