All decoupling capacitors (0.1 μF and 0.01
μF) are placed on the pad adjacent to the BGA via of the corresponding pin, as shown in
Figure 2-1. At least one of the capacitors (0.1 μF and 0.01 μF) must be placed for
each SerDes bank. The capacitor pad to via trace must be small.
The bypass capacitor (10 μF) must be placed
at the edge of the IC.
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