67.12 POR Characteristics

The figure below provides a general presentation of Power-On-Reset (POR) characteristics.

Figure 67-9. General Presentation of POR Behavior

When a very slow (versus t_RST) supply rising slope is applied on the POR VDD pin, the reset time becomes negligible and the reset signal is released when VDD raises higher than V_T+.

When a very fast (versus t_RST) supply rising slope is applied on the POR VDD pin, the voltage threshold becomes negligible and the reset signal is released after t_RST. It is the smallest possible reset time.

Table 67-41. VDDBU Power-On Reset Characteristics
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V_T+	Threshold Voltage Rising	–	1.3	–	1.5	V
V_T-	Threshold Voltage Falling	–	1.22	–	1.4	V
V_hys	Hysteresis Voltage	–	50	–	160	mV
t_RST	Reset Timeout Period	–	890	–	5100	µs

Table 67-42. VDDCORE Power-On Reset Characteristics
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V_T+	Threshold Voltage Rising	–	0.927	–	1.075	V
V_T-	Threshold Voltage Falling	–	0.848	–	1.025	V
V_hys	Hysteresis Voltage	–	38	–	109	mV
t_RST	Reset Timeout Period	–	150	–	650	µs

Table 67-43. VDDANA Power-On Reset Characteristics
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V_T+	Threshold Voltage Rising	–	1.3	–	1.5	V
V_T-	Threshold Voltage Falling	–	1.22	–	1.4	V
V_hys	Hysteresis Voltage	–	50	–	160	mV
t_RST	Reset Timeout Period	–	130	–	650	µs