67.12 POR Characteristics

The figure below provides a general presentation of Power-On-Reset (POR) characteristics.

Figure 67-9. General Presentation of POR Behavior

When a very slow (versus tRST) supply rising slope is applied on the POR VDD pin, the reset time becomes negligible and the reset signal is released when VDD raises higher than VT+.

When a very fast (versus tRST) supply rising slope is applied on the POR VDD pin, the voltage threshold becomes negligible and the reset signal is released after tRST. It is the smallest possible reset time.

Table 67-41. VDDBU Power-On Reset Characteristics
SymbolParameterConditionsMinTypMaxUnit
VT+Threshold Voltage Rising1.31.5V
VT-Threshold Voltage Falling1.221.4V
VhysHysteresis Voltage50160mV
tRSTReset Timeout Period8905100µs
Table 67-42. VDDCORE Power-On Reset Characteristics
SymbolParameterConditionsMinTypMaxUnit
VT+Threshold Voltage Rising0.9271.075V
VT-Threshold Voltage Falling0.8481.025V
VhysHysteresis Voltage38109mV
tRSTReset Timeout Period150650µs
Table 67-43. VDDANA Power-On Reset Characteristics
SymbolParameterConditionsMinTypMaxUnit
VT+Threshold Voltage Rising1.31.5V
VT-Threshold Voltage Falling1.221.4V
VhysHysteresis Voltage50160mV
tRSTReset Timeout Period130650µs