33.16.2.1 Configuration Procedure

Before configuring the asynchronous partial wake-up function of a peripheral, check that the peripheral clock is enabled (PMC_PCSRx.PIDx must be set).

The procedure to enable the asynchronous partial wake-up function of a peripheral is the following:

1. Check that the corresponding PIDx bit in the PMC Asynchronous Partial Wake-Up Activity Status register (PMC_SLPWK_ASR) is cleared. This ensures that the peripheral has no activity in progress.
2. Enable the asynchronous partial wake-up function of the peripheral by writing a one to the corresponding PIDx bit in PMC_SLPWK_ER.
3. Check that the corresponding PIDx bit in PMC_SLPWK_ASR is cleared. This ensures that no activity has started during the enable phase.

   If the PIDx bit is set, proceed to the next step.

   If the PIDx bit is cleared, asynchronous partial wake-up mode is active for the peripheral. Before entering ULP1 mode, check that the AIP bit in the PMC Asynchronous Partial Wake-Up Activity In Progress register (PMC_SLPWK_AIPR) is cleared. This ensures that none of the peripherals has any activity in progress. The system can now be placed in ULP1 mode.

4. In PMC_SLPWK_ASR, if the corresponding PIDx bit is set, the asynchronous partial wake-up function must be immediately disabled by writing a one to the PIDx bit in the PMC Asynchronous Partial Wake-Up Disable register (PMC_SLPWK_DR). Wait for the end of peripheral activity before reinitializing the procedure.