QSPI NOR memories without SFDP
This section only applies when the ROM code fails to read the SFDP tables from the QSPI NOR memory.
The ROM code reads the JEDEC ID of the QSPI NOR memory, and then selects the read settings based on the manufacturer ID (first byte of the JEDEC ID) from the following hard-coded values:
| Cypress (01h) | Micron (20h) | Macronix (C2h) | Winbond (EFh) | Others | |
|---|---|---|---|---|---|
| Fast Read protocol | SPI 1-4-4 | SPI 1-4-4 | SPI 1-4-4 | SPI 1-4-4 | SPI 1-1-1 |
| Fast Read op code | EBh | EBh | EBh | EBh | 0Bh |
| Address width | 24 bits | 24 bits | 24 bits | 24 bits | 24 bits |
| Number of mode clock cycles | 2 | 1 | 2 | 2 | 0 |
| Number of wait states | 4 | 9 | 4 | 4 | 8 |
| Value of mode cycles to enter the 0-4-4 mode (XIP) | A0h | 0h The ROM code first sets XIP bit[3] in the Volatile Configuration Register (VCR) | 0Fh | A5h | N/A |
| Value of mode cycles to exit the 0-4-4 mode (normal read) | 00h | 1h | 00h | FFh | N/A |
| XIP supported | Yes | Yes | Yes | Yes | No |
Those hard-coded parameters give a last chance to the ROM code to boot from a QSPI NOR memory in either normal mode or XIP (continuous read) mode.