15.8.7 AHB Mask
| Name: | AHBMASK |
| Offset: | 0x14 |
| Reset: | 0x0000007F |
| Property: | Write-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NVMCTRL | DSU | HPB2 | HPB1 | HPB0 | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 1 | 1 | 1 | 1 |
Bit 4 – NVMCTRL NVMCTRL AHB Clock Mask
| Value | Description |
|---|---|
| 0 | The AHB clock for the NVMCTRL is stopped. |
| 1 | The AHB clock for the NVMCTRL is enabled. |
Bit 3 – DSU DSU AHB Clock Mask
| Value | Description |
|---|---|
| 0 | The AHB clock for the DSU is stopped. |
| 1 | The AHB clock for the DSU is enabled. |
Bit 2 – HPB2 HPB2 AHB Clock Mask
| Value | Description |
|---|---|
| 0 | The AHB clock for the HPB2 is stopped. |
| 1 | The AHB clock for the HPB2 is enabled. |
Bit 1 – HPB1 HPB1 AHB Clock Mask
| Value | Description |
|---|---|
| 0 | The AHB clock for the HPB1 is stopped. |
| 1 | The AHB clock for the HPB1 is enabled. |
Bit 0 – HPB0 HPB0 AHB Clock Mask
| Value | Description |
|---|---|
| 0 | The AHB clock for the HPB0 is stopped. |
| 1 | The AHB clock for the HPB0 is enabled. |