15.8.11 Interrupt Enable Clear
| Name: | INTENCLR |
| Offset: | 0x34 |
| Reset: | 0x00 |
| Property: | Write-Protected |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CFD | CKRDY | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – CFD Clock Failure Detector Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Clock Failure Detector Interrupt Enable bit and the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Clock Failure Detector interrupt is disabled. |
| 1 | The Clock Failure Detector interrupt is enabled and will generate an interrupt request when the Clock Failure Detector Interrupt flag is set. |
Bit 0 – CKRDY Clock Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Clock Ready interrupt is disabled. |
| 1 | The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock Ready Interrupt flag is set. |