15.8.13 Interrupt Flag Status and Clear
| Name: | INTFLAG |
| Offset: | 0x36 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CFD | CKRDY | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – CFD Clock Failure Detector Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Clock Failure Detector Interrupt Enable bit and the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Clock Failure Detector interrupt is disabled. |
| 1 | The Clock Failure Detector interrupt is enabled and will generate an interrupt request when the Clock Failure Detector Interrupt flag is set. |
Bit 0 – CKRDY Clock Ready
This flag is cleared by writing a one to the flag.
This flag is set when the synchronous CPU and APBx clocks have frequencies as indicated in the CPUSEL and APBxSEL registers, and will generate an interrupt if INTENCLR/SET.CKRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Clock Ready Interrupt flag.