34.10.4 Analog-to-Digital (ADC) Characteristics

Table 34-19. Operating Conditions
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
RES	Resolution	-	8	-	12	bits
f_{CLK_ADC}	ADC Clock frequency	-	120	-	2100	kHz
	Sample rate⁽¹⁾	Single shot	20	-	300	ksps
	Sample rate⁽¹⁾	Free running	20	-	350 ⁽³⁾	ksps
	Sampling time ⁽¹⁾	-	250	-	-	ns
	Sampling time with DAC as input⁽²⁾	-	3	-	-	µs
	Sampling time with Temp sens as input⁽²⁾	-	10	-	-	µs
	Sampling time with Bandgap as input⁽²⁾	-	10	-	-	µs
	Conversion time - Differential mode	Gain: x1 ⁽¹⁾	-	6	-	cycles
		Gain: x0.5, x2, x4 ⁽²⁾	-	7	-
		Gain: x8, x16 ⁽²⁾		8	-
	Conversion time - Single Ended mode	Gain: x1 ⁽¹⁾	-	7	-	cycles
		Gain: x0.5, x2, x4 ⁽²⁾	-	8	-
		Gain: x8, x16 ⁽²⁾	-	9	-
V_REF	Voltage reference range (VREFA or VREFB)	-	2.0	-	V_DDANA-0.6	V
INT1V	Internal 1V reference ^(2,4)	-	-	1.0	-	V
INTVCC0	Internal ratiometric reference 0⁽²⁾	2.7V < V_DDANA < 3.63V	-	V_DDANA/1.48	-	V
INTVCC0 Voltage Error	Internal ratiometric reference 0 error⁽²⁾	2.7V < V_DDANA<3.63V	-1.0	-	+1.0	%
INTVCC1	Internal ratiometric reference 1⁽²⁾	2.7V < V_DDANA < 3.63V	-	V_DDANA/2	-	V
INTVCC1 Voltage Error	Internal ratiometric reference 1 error ⁽²⁾	2.7V < V_DDANA < 3.63V	-1.0	-	+1.0	%
	Conversion range ⁽¹⁾	Differential mode	-V_REF/GAIN	-	+V_REF/GAIN	V
	Conversion range ⁽¹⁾	Single-ended mode	0.0	-	+V_REF/GAIN	V
C_SAMPLE	Sampling capacitance ⁽²⁾		-	3.5	-	pF
R_SAMPLE	Input channel source resistance ⁽²⁾		-	-	3.5	kΩ
I_DD	DC supply current ⁽¹⁾	f_{CLK_ADC} = 2.1 MHz ⁽³⁾	-	1.25	4.7	mA

Note:

These values are based on characterization and not covered by test limits in production.
These values are based on simulation, are not covered by test limits in production or characterization.
In this condition and for a sample rate of 350 ksps, a conversion takes 6 clock cycles of the ADC clock (conditions: 1X gain, 12-bit resolution, differential mode, free-running).
It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.

Table 34-20. Differential Mode ^(2,4)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
ENOB	Effective Number Of Bits	1x Gain, Ext. Ref. 2V ≤ VREF ≤ 3V⁽¹⁾	9.9	10.7	10.8	bits
TUE	Total Unadjusted Error	1x Gain, Ext. Ref. 2V ≤ VREF ≤ 3V⁽¹⁾	0.8	3.1	9.9	LSB
		1x Gain, VREF = V_DDANA/1.48⁽¹⁾	2.3	6.9	15	LSB
		1x Gain, VREF = INT1V	4.0	8.6	32	LSB
INL	Integral Non Linearity	1x Gain, Ext. Ref. 2V ≤ VREF ≤ 3V⁽¹⁾	0.67	0.98	1.6	LSB
		1x Gain, VREF = V_DDANA/1.48⁽¹⁾	0.70	1.1	1.7	LSB
		1x Gain, VREF = INT1V	1.2	1.8	3	LSB
DNL	Differential Non Linearity	1x Gain, Ext. Ref. 2V ≤ VREF ≤ 3V⁽¹⁾	+/-0.4	+/-0.6	+/-0.8	LSB
		1x Gain, VREF = V_DDANA/1.48⁽¹⁾	+/-0.5	+/-0.7	+/-0.9	LSB
		1x Gain, VREF = INT1V	+/-0.6	+/-0.8	+/-3	LSB
GE	Gain Error	1x Gain, Ext. Ref. 2V ≤ VREF ≤ 3V⁽¹⁾	-13	-3.6	+9	mV
		1x Gain, VREF = V_DDANA/1.48⁽¹⁾	-36	-10.6	+22	mV
		1x Gain, VREF = INT1V	-29	-2.7	+18	mV
	Gain Accuracy⁽³⁾	0.5x Gain, Ext. Ref. 2V ≤ VREF ≤ 3V⁽¹⁾	+/-0.1	+/-0.2	+/-0.3	%
	Gain Accuracy⁽³⁾	2x to 16x Gain, Ext. Ref. 2V ≤ VREF ≤ 3V⁽¹⁾	+/-0.1	+/-0.4	+/-0.6	%
OE	Offset Error	1x Gain, Ext. Ref. 2V ≤ VREF ≤ 3V⁽¹⁾	-6	2.3	+10	mV
		1x Gain, VREF = V_DDANA/1.48⁽¹⁾	-5	1.6	+10	mV
		1x Gain, VREF = INT1V	-4	2.1	+10	mV
SFDR	Spurious Free Dynamic Range	1x Gain Ext. Ref 2V ≤ VREF ≤ 3V F_{CLK_ADC} = 2.1 MHz F_IN = 40 kHz A_IN = 95% FSR	77	85	87	dB
SINAD	Signal-to-Noise and Distortion		61	53	67	dB
SNR	Signal-to-Noise Ratio		63	54	69	dB
THD	Total Harmonic Distortion		-73	-71	-64	dB
	Noise RMS	Ta = 25°C	0.6	1	2.5	mV

Note:

Specifications are based on characterization and not covered by production screening.
Respect the input common mode voltage through the following equations (where, VCM_IN is the input channel common mode voltage):
1. If |VIN| > VREF/4
  VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
  VCM_IN > VREF/4 -0.05*VDDANA -0.1V
2. If |VIN| < VREF/4
  VCM_IN < 1.2*VDDANA - 0.75V
  VCM_IN > 0.2*VDDANA - 0.1V
The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (2*Vref/GAIN).
With gain compensation enabled (REFCTRL.REFCOMP = 1).

Table 34-21. Single-Ended Mode ^(1,2,4)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
ENOB	Effective Number of Bits	1x Gain, Ext. Ref. 2V ≤ VREF≤ 3V	8.9	9.9	10.1	Bits
TUE	Total Unadjusted Error	1x Gain, Ext. Ref. 2V ≤ VREF ≤ 3V	1.6	7	22	LSB
INL	Integral Non-Linearity	1x Gain, Ext. Ref. 2V ≤ VREF ≤ 3V	1.0	1.5	3.0	LSB
DNL	Differential Non-Linearity	1x Gain, Ext. Ref. 2V ≤ VREF≤ 3V	±0.5	±0.8	±0.95	LSB
GE	Gain Error	1x Gain, Ext. Ref. 2V ≤ VREF ≤ 3V	-7.1	-0.3	7.1	mV
	Gain Accuracy ⁽³⁾	0.5x Gain, Ext. Ref. 2V ≤ VREF≤ 3V	±0.1	±0.2	±0.4	%
	Gain Accuracy ⁽³⁾	2x to 16x Gain, Ext. Ref. 2V ≤ VREF≤ 3V	±0.2	±0.6	±0.9	%
OE	Offset Error	1x Gain, Ext. Ref. 2V ≤ VREF ≤ 3V	-9	5.5	28	mV
SFDR	Spurious Free Dynamic Range	1x Gain Ext. Ref. 2V ≤ VREF ≤ 3V F_{CLK_ADC} = 2.1 MHz F_IN = 40 kHz A_IN = 95% FSR	70	80	84	dB
SINAD	Signal-to-Noise and Distortion		56	61	62	dB
SNR	Signal-to-Noise Ratio		58	63	64	dB
THD	Total Harmonic Distortion		-68	-67	-59	dB
	Noise RMS	T = 25°C	-	1	6	mV

Note:

Specifications are based on characterization and not covered by production screening.
Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage) for all VIN:
VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (V_REF/GAIN).
With gain compensation enabled (REFCTRL.REFCOMP = 1)