17.6.11 Clock Status
Note: The corresponding RDY bits are updated only after clock switch request is
initiated via OSCCON.NOSC[3:0].
| Name: | CLKSTAT |
| Offset: | 0x170 |
| Reset: | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPLL3RDY | LPRCRDY | SOSCRDY | POSCRDY | SPLL1RDY | FRCRDY | ||||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 5 – SPLL3RDY System PLL (Clock-3) Ready Status value
| Value | Description |
|---|---|
| 1 | SPLL_CLK3 is stable and ready |
| 0 | SPLL_CLK3 is not stable and not ready |
Bit 4 – LPRCRDY LPRC Ready Status value
| Value | Description |
|---|---|
| 1 | LPRC is stable and ready |
| 0 | LPRC is not stable and not ready |
Bit 3 – SOSCRDY SOSC Ready Status value
| Value | Description |
|---|---|
| 1 | SOSC is stable and ready |
| 0 | SOSC is not stable and not ready |
Bit 2 – POSCRDY Primary Oscillator Ready Status value
| Value | Description |
|---|---|
| 1 | POSC is stable and ready |
| 0 | POSC is not stable and not ready |
Bit 1 – SPLL1RDY System PLL (Clock-1) Ready Status value
| Value | Description |
|---|---|
| 1 | SPLL_CLK1 is stable and ready |
| 0 | SPLL_CLK1 is not stable and not ready |
Bit 0 – FRCRDY FRC Ready Status value
| Value | Description |
|---|---|
| 1 | FRC is stable and ready |
| 0 | FRC is not stable and not ready |