17.6.3 SPLL Control

Note: Perform the system unlock sequence before this register is written.
Name: SPLLCON
Offset: 0x20
Reset: 0xC0010028

Bit 3130292827262524 
 SPLL_BYP[1:0]       
Access R/W/LR/W/L 
Reset 11 
Bit 2322212019181716 
     SPLL2POSTDIV2[3:0] 
Access R/W/LR/W/LR/W/LR/W/L 
Reset 0001 
Bit 15141312111098 
 SPLL1POSTDIV1[7:0] 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 00000000 
Bit 76543210 
    SPLLFLOCKSPLLPWDN    
Access R/W/LR/W/L 
Reset 01 

Bits 31:30 – SPLL_BYP[1:0] SPLL Bypass; SPLL_CLK2 clock source selection

Note:
  • Dictates the clock source for ADC CP (Analog-to-Digital Converter Charge Pump) (SPLL_CLK2) Clock generation only
  • Preselect the clock sources and keep them ready before the need of ADC CP arrives. Failure to do so results in loss of clock for one or two cycles when ADC CP is enabled.
ValueDescription
00RFPLL Clock is the clock source for ADC CP Clock Generation.
x1FRC is used as clock source for ADC CP Clock Generation.
10POSC is used as clock source for ADC CP Clock Generation.

Bits 19:16 – SPLL2POSTDIV2[3:0] ADC-CP (SPLL2) Post Divide Value

ValueDescription
1 ≤ SPLLPOSTDIV2 ≤ 15Divide by SPLL2POSTDIV2
0No Clock; Clock disabled

Bits 15:8 – SPLL1POSTDIV1[7:0] SPLL1 Post Divide Value

ValueDescription
2 ≤ SPLLPOSTDIV ≤ 255Divide by SPLL1POSTDIV1
0,1Divide by 1

Bit 4 – SPLLFLOCK System PLL Force Lock

ValueDescription
1Force the SPLL lock signal to be asserted
0Do not force the SPLL lock signal to be asserted

Bit 3 – SPLLPWDN PLL Power Down Register bit

ValueDescription
1PLL is powered down
0PLL is active