26.8.4 CLCxSEL1

Generic CLCx Data 2 Select Register

Name:	CLCxSEL1
Address:	0xE2A,0xE34,0xE3E,0xE48,0xE52,0xE5C,0xE66,0xE70

Bits 5:0 – D2S[5:0] CLCx Data 2 Input Selection bits


DyS Value	CLC Input Source	DyS Value	CLC Input Source
`111111` [63]	Reserved	`011111` [31]	IOC_flag
`111110` [62]	Reserved	`011110` [30]	ZCD_out
`111101` [61]	Reserved	`011101` [29]	CMP2_out
`111100` [60]	Reserved	`011100` [28]	CMP1_out
`111011` [59]	Reserved	`011011` [27]	PWM4_out
`111010` 58]	Reserved	`011010` [26]	PWM3_out
`111001` [57]	Reserved	`011001` [25]	CCP2_out
`111000` [56]	Reserved	`011000` [24]	CCP1 _out
`110111` [55]	Reserved	`010111` [23]	TMR6_out
`110110` [54]	Reserved	`010110` [22]	TMR5 _overflow
`110101` [53]	Reserved	`010101` [21]	TMR4 _out
`110100` [52]	Reserved	`010100` [20]	TMR3 _overflow
`110011` [51]	Reserved	`010011` [19]	TMR2 _out
`110010` [50]	CWG1B_out	`010010` [18]	TMR1 _overflow
`110001` [49]	CWG1A_out	`010001` [17]	TMR0 _overflow
`110000` [48]	SCK2	`010000` [16]	CLKR _out
`101111` [47]	SDO2	`001111` [15]	ADCRC
`101110` [46]	SCK1	`001110` [14]	SOSC
`101101` [45]	SDO1	`001101` [13]	SFINTOSC (1MHz)
`101100` [44]	EUSART2_TX/CK_out	`001100` [12]	MFINTOSC (32 kHz)
`101011` [43]	EUSART2_DT_out	`001011` [11]	MFINTOSC (500 kHz)
`101010` [42]	EUSART1_TX/CK_out	`001010` [10]	LFINTOSC
`101001` [41]	EUSART1_DT_out	`001001` [9]	HFINTOSC
`101000` [40]	CLC8_out	`001000` [8]	F_OSC
`100111` [39]	CLC7_out	`000111` [7]	CLCIN7PPS
`100110` [38]	CLC6_out	`000110` [6]	CLCIN6PPS
`100101` [37]	CLC5_out	`000101` [5]	CLCIN5PPS
`100100` [36]	CLC4_out	`000100` [4]	CLCIN4PPS
`100011` [35]	CLC3_out	`000011` [3]	CLCIN3PPS
`100010` [34]	CLC2_out	`000010` [2]	CLCIN2PPS
`100001` [33]	CLC1_out	`000001` [1]	CLCIN1PPS
`100000` [32]	DSM1_out	`000000` [0]	CLCIN0PPS

Reset States:

POR/BOR = xxxxxx

All Other Resets = uuuuuu