11.5.4 Interrupt Control
| Name: | INTCTRL |
| Offset: | 0x04 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLREADY | EEREADY | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – FLREADY Flash Ready Interrupt
Writing a ‘1’ to this bit enables the interrupt indicating that
the Flash is ready for new write/erase operations.
This is a level interrupt that will be triggered only when the FLREADY bit in the
INTFLAGS register is set to ‘1’. The interrupt must be disabled
in the interrupt handler before triggering a Flash write/erase operation, as the
FLREADY bit will not be cleared before this command is issued.
Bit 0 – EEREADY EEPROM Ready Interrupt
Writing a ‘1’ to this bit enables the interrupt indicating that
the EEPROM is ready for new write/erase operations.
This is a level interrupt that will be triggered only when the EEREADY bit in the
INTFLAGS register is set to ‘1’. The interrupt must be disabled
in the interrupt handler before triggering an EEPROM write/erase operation, as
the EEREADY bit will not be cleared before this command is issued.