39.18 ADC

Table 39-24. ADC Accuracy Specifications
Operating Conditions: V_DD = 3.0V V_ADCREF = 3.0V T_A = 25°C ADC in single ended conversion mode f_{CLK_ADC} = 500 kHz
Symbol	Description	Min.	Typ. ✝	Max.	Unit	Conditions
N_R	Resolution	—	—	12	bit
E_INL	Integral non-linearity error	-1.8	0.1	1.8	LSb
E_DNL⁽¹⁾	Differential non-linearity error	-1	0.1	1	LSb
E_OFF	Offset error	-5	2.5	5	LSb
E_GAIN	Gain error	-5	1.5	5	LSb
V_ADCREF *	ADC reference voltage	1.024	—	V_DD	V	f_{CLK_ADC} ≤ 500 kHz
V_ADCREF *	ADC reference voltage	1.8	—	V_DD	V	125 kHz ≤ f_{ADC_CLK} ≤ 2 MHz
V_AIN	Full-scale range	GND	—	V_ADCREF	V
Z_AIN	Recommended impedance of analog voltage source	—	10	—	kΩ
R_VREFA⁽²⁾	ADC voltage reference ladder impedance	—	50	—	kΩ
	V_DD/10 divider accuracy (VDDDIV10 / VDDIO2DIV10)	—	±10	—	%	Measured with ADC using on-chip internal reference
✝ Data found in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested. * These parameters are characterized but not tested in production. Note: The ADC conversion result never decreases with an increase in the input and has no missing codes. This is the impedance seen by the VREFA pin when the external reference is selected.

Table 39-25. ADC Conversion Timing Specifications
Operating Conditions: V_DD = 3.0V V_ADCREF = 3.0V T_A = 25°C
Symbol	Description	Min.	Typ. ✝	Max.	Unit	Conditions
T_{CLK_ADC}*	ADC clock period	1	—	8	μs
t_CNV	Conversion time	—	13.5T_{CLK_ADC} + 2T_{CLK_PER}	—
f_ADC*	Sample rate	8	—	130	ksps
t_SENSE	Delay for changing MUXPOS to TEMP	—	40	—	μs
t_{ADC_INIT}	ADC Initialization time	—	6	—	μs
t_{ADC_DACREF}	ADC sampling time with DACREFn as input for MUXPOS	—	30	—	μs
✝ Data found in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested. * These parameters are characterized but not tested in production.