39.8 Memory Programming Specifications

Table 39-7. Memory Programming Specifications
Symbol	Description	Min.	Typ.✝	Max.	Unit	Conditions
Data EEPROM Memory Specifications
E_D*	Data EEPROM byte endurance	100k	—	—	Erase/Write cycles	-40°C ≤ T_A ≤ +85°C
t_{D_RET}	Characteristic retention	—	40	—	Year
V_{D_RW}	V_DD for Read or Erase/Write operation	V_DDMIN	—	V_DDMAX	V
N_{D_REF}*	Total Erase/Write cycles before refresh⁽²⁾	1M	4M	—	Erase/Write cycles	-40°C ≤ T_A ≤ +85°C
t_{D_CE}	Byte/Multibyte/Full EEPROM Erase time	—	10	11.7	ms
t_{D_WRE}	Byte Write time	—	70	75	μs
t_{D_BEW}	Byte Erase and Write time	—	10.07	—	ms
Program Flash Memory Specifications
E_P*	Flash memory cell endurance	1k	—	—	Erase/Write cycles
t_{P_RET}	Characteristic retention	—	40	—	Year
V_{P_RD}	V_DD for Read operation	V_DDMIN	—	V_DDMAX	V
V_{P_REW}	V_DD for Erase/Write operation	V_BOD⁽¹⁾	—	V_DDMAX	V
t_{P_CE}	Chip Erase time	—	11	11.6	ms
t_{P_PE}	Page Erase time	—	10	11.7	ms
t_{P_WRD}	Byte/Word Write time	—	70	75	μs
✝ Data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only. * These parameters are characterized but not tested in production. Note: During Chip Erase, the Brown-out Detector (BOD) configured with BODLEVEL0 is forced ON. The erase attempt will fail if the supply voltage V_DD is below V_BOD for BODLEVEL0. The number of times a separate location may be erased/written before a full refresh (erase/write) of the EEPROM array is required.

Data EEPROM Memory Specifications

E_D*

Data EEPROM byte endurance

100k

—

Erase/Write cycles

-40°C ≤ T_A ≤ +85°C

t_{D_RET}

Characteristic retention

—

40

—

Year

V_{D_RW}

V_DD for Read or Erase/Write operation

V_DDMIN

—

V_DDMAX

V

N_{D_REF}*

Total Erase/Write cycles before refresh⁽²⁾

1M

4M

—

Erase/Write cycles

-40°C ≤ T_A ≤ +85°C

t_{D_CE}

Byte/Multibyte/Full EEPROM Erase time

—

10

11.7

ms

t_{D_WRE}

Byte Write time

—

70

75

μs

t_{D_BEW}

Byte Erase and Write time

—

10.07

—

ms

Program Flash Memory Specifications

E_P*

Flash memory cell endurance

1k

—

Erase/Write cycles

t_{P_RET}

Characteristic retention

—

40

—

Year

V_{P_RD}

V_DD for Read operation

V_DDMIN

—

V_DDMAX

V

V_{P_REW}

V_DD for Erase/Write operation

V_BOD⁽¹⁾

—

V_DDMAX

V

t_{P_CE}

Chip Erase time

—

11

11.6

ms

t_{P_PE}

Page Erase time

—

10

11.7

ms

t_{P_WRD}

Byte/Word Write time

—

70

75

μs

✝ Data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

* These parameters are characterized but not tested in production.

Note:

During Chip Erase, the Brown-out Detector (BOD) configured with BODLEVEL0 is forced ON. The erase attempt will fail if the supply voltage V_DD is below V_BOD for BODLEVEL0.
The number of times a separate location may be erased/written before a full refresh (erase/write) of the EEPROM array is required.