IS2083

7.3.4.2 Entering Debug Mode

Debug mode is entered by using the CPU 2-wire Test Mode Entry interface. On entry into Debug mode, the OCI holds the CPU and Watchdog Timer in the Reset state using JReset until the external debugger asserts DebugReq using the DebugReqOn JTAG instruction. This allows the debugger to configure the device before the CPU boots-up.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.