5.5.2.3 I2SC Initialization

The following code snippet initializes the I2SC0 interface.

/* Enable system clock for I2SC0 */
PMC->PMC_PCR = PMC_PCR_PID(ID_I2SC0) 
                | PMC_PCR_CMD
                | PMC_PCR_EN;     
  
/* Perform software reset of I2SC0 peripheral */ 
I2SC0->I2SC_CR = I2SC_CR_SWRST;       

/* Configure I2SC0 parameters */
I2SC0->I2SC_MR = I2SC_MR_MODE_SLAVE
                    | I2SC_MR_DATALENGTH_32_BITS
                    | I2SC_MR_FORMAT_I2S;

/* Enable I2SC0 transmitter */ 
I2SC0->I2SC_CR = I2SC_CR_TXEN;  
     
/* Wait until transmitter is enabled */ 
while(!(I2SC0->I2SC_SR & I2SC_SR_TXEN)); 

/* Enable DMA channel */ 
XDMAC1->XDMAC_GE = XDMAC_GE_EN0;  
     
/* Wait until DMA transfer is done */
while(!(XDMAC1->XDMAC_CHID[0].XDMAC_CIS & XDMAC_CIS_BIS));

I2SC0 is used for this example, which is configured in Slave mode to accept the bit clock and the LR clock, with one LR clock period containing 64 bit clocks. A 12.288 MHz signal generated using the Audio PLL is fed through the CLK_AUDIO pin as the master clock for the AD1934. The AD1934 is configured to generate the bit clock and the LR clock and received data samples from the I2SC0 slave. Data is sent as a 32-bit word with the original 16-bit audio data placed in the 16 MSB bits and the 16 LSB bits left at 0.

I2SC0 is not clocked from the Audio PLL clock in this case, and it is sufficient to clock it with the default power manager system clock.

The I2SC0 transmitter is enabled, along with the DMA channel, to start the transfer.