5.5.1 I2SC Master Mode Code Example
This code example configures the I2SC0 in Master mode to generate the master clock, the bit clock, and the LR clock and to transmit the data to the AD1934 DAC.
The 12.288 MHz master clock is generated from the I2SC module and fed to the MCLKI pin of
the AD1934. The AD1934 is configured with a sample rate set to 48 kHz and accepts the LR
clock and bit clock from the external master (I2SC). The word width of the AD1934 is
always 32 bits and is left-justified with MSB first. It is configured to accept audio
data in the I2S frame format. The following are the register settings for the AD1934,
configured using the SPI interface:
- PLL and Clock Control 0 --> 0x98
- DAC Control 2 --> 0x18
Other registers of the AD1934 are left at their default reset values.
The audio PLL output is used to clock the I2SC0 module through the GCLK interface. The steps given in section Audio PLL Initialization can be used for this example.
The following sections provide the code snippet to configure the I2SC I/O pins, the DMA channel and the I2SC peripheral.