5.5.2 I2SC Slave Mode Code Example

This code example configures the I2SC0 in Slave mode, which accepts the bit clock and the LR clock and transmits the data to the AD1934 DAC.

The 12.288 MHz master clock is generated from the Audio PLL as in section Code Example - Audio PLL. The generated 12.288 MHz signal from the CLK_AUDIO pin is fed to the MCLKI pin of the AD1934. The AD1934 is configured to generate the bit clock and LR clock with a sample rate set to 48 kHz. The word width of the AD1934 is always 32 bits and is configured to accept audio data in I2S frame format and left-justified with MSB first. The following are the register settings for the AD1934, which is configured using the SPI interface.
  • PLL and Clock Control 0 --> 0x98
  • DAC Control 1 --> 0x70
  • DAC Control 2 --> 0x18

Other registers of AD1934 are left to their default reset values.

The same Audio PLL initialization steps given in the section "Code Example - Audio PLL" can be used for this example.

The following sections provide the code snippet to configure the I2SC I/O pins, the DMA channel and the I2SC peripheral.