5.5.1.3 I2SC Initialization

The following code snippet initializes the I2SC0 interface.

/* Enable Audio PLL as source for I2SC0 through GCLK */
PMC->PMC_PCR = PMC_PCR_PID(ID_I2SC0) 
                | PMC_PCR_GCKCSS_AUDIO_CLK
                | PMC_PCR_GCKDIV(1)
                | PMC_PCR_CMD
                | PMC_PCR_EN
                | PMC_PCR_GCKEN; 

/* Wait until GCLK is ready */
while (!(PMC->PMC_SR & PMC_SR_GCKRDY));

/* Select GCLK as clock source for I2SC0 in SFR module */ 
SFR->SFR_I2SCLKSEL = SFR_I2SCLKSEL_CLKSEL0;     
  
/* Perform software reset of I2SC0 peripheral */ 
I2SC0->I2SC_CR = I2SC_CR_SWRST;       

/* Configure I2SC0 parameters */
I2SC0->I2SC_MR = I2SC_MR_MODE_MASTER
                    | I2SC_MR_DATALENGTH_32_BITS
                    | I2SC_MR_FORMAT_I2S
                    | (3u << 16)
                    | I2SC_MR_IMCKFS(31)
                    | I2SC_MR_IMCKMODE;

/* Enable I2SC0 master clock and transmitter */ 
I2SC0->I2SC_CR = I2SC_CR_CKEN | I2SC_CR_TXEN;  
     
/* Wait until transmitter is enabled */ 
while(!(I2SC0->I2SC_SR & I2SC_SR_TXEN)); 

/* Enable DMA channel */ 
XDMAC1->XDMAC_GE = XDMAC_GE_EN0;  
     
/* Wait until DMA transfer is done */
while(!(XDMAC1->XDMAC_CHID[0].XDMAC_CIS & XDMAC_CIS_BIS));

I2SC0 is used for this example, which is configured in Master mode to generate the master clock, the bit clock and the LR clock, with one LR clock period containing 64-bit clocks. The AD1934 should be configured to accept all these clocks along with the data. Data is sent as a 32-bit word with the original 16-bit audio data placed in the 16 MSB bits and the 16 LSB bits left as 0.

The 98.304 MHz output from the Audio PLL is divided by 2 by the GCLK controller, and this GCLK output (49.152 MHz) is selected as the clock source for the I2SC0 module in the Special Function Register (SFR_I2SCLKSEL).

The master clock divider in I2SC0 is enabled with the master clock division factor set to 4, which generates (49.152 / 4) = 12.288 MHz on the I2SCMCK pin.

The bit clock division factor is calculated as (49.152MHz / (48000 * 2 * 16)) = 32, so IMCKFS is set to 31.

The master clock and the I2SC0 transmitter are enabled, along with the DMA channel, to start the transfer.