14.8.4 TRX_CTRL_1
| Name: | TRX_CTRL_1 |
| Offset: | 0x04 |
| Reset: | 0x22 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PA_EXT_EN | IRQ_2_EXT_EN | TX_AUTO_CRC_ON | RX_BL_CTRL | SPI_CMD_MODE[1:0] | IRQ_MASK_MODE | IRQ_POLARITY | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | |
Bit 7 – PA_EXT_EN PA_EXT_EN
The register bit PA_EXT_EN enables RF front-end control signals DIG3 and DIG4 to indicate the transmit state of the radio transceiver.
| PA_EXT_EN | State | Signal | Value | Description |
|---|---|---|---|---|
| 0x0 | N/A | DIG3 | L | External RF front-end control disabled |
| DIG4 | L | |||
| 0x1(1) | TX_BUSY | DIG3 | H | External RF front-end control enabled |
| DIG4 | L | |||
| Other | DIG3 | L | ||
| DIG4 | H |
- It is recommended to set PA_EXT_EN = 1 only in receive or transmit states to reduce the power consumption or avoid leakage current of external RF switches or other building blocks, especially during SLEEP or DEEP_SLEEP state.
Bit 6 – IRQ_2_EXT_EN IRQ_2_EXT_EN
The register bit IRQ_2_EXT_EN controls external signaling for time stamping via DIG2.
| Value | Description |
|---|---|
| 0x0 | Time stamping over pin 10 (DIG2) is disabled |
| 0x1(1) | Time stamping over pin 10 (DIG2) is enabled |
- The pin 10 (DIG2) is also active if the corresponding interrupt event IRQ_2 (RX_START) mask bit in register 0x0E (IRQ_MASK) is set to zero.
The timing of a received frame can be determined by a separate pin 10 (DIG2). If register bit IRQ_2_EXT_EN is set to one, the reception of a PHR field is directly issued on pin 10 (DIG2), similar to interrupt IRQ_2 (RX_START).
Bit 5 – TX_AUTO_CRC_ON TX_AUTO_CRC_ON
The register bit TX_AUTO_CRC_ON controls the automatic FCS generation for transmit operations.
| Value | Description |
|---|---|
| 0x0 | Automatic FCS generation is disabled |
| 0x1 | Automatic FCS generation is enabled |
- The TX_AUTO_CRC_ON function can be used within Basic and Extended Operating Modes.
Bit 4 – RX_BL_CTRL RX_BL_CTRL
The register bit RX_BL_CTRL controls the Frame Buffer Empty Indicator.
| Value | Description |
|---|---|
| 0x0 | Frame Buffer Empty Indicator disabled |
| 0x1 | Frame Buffer Empty Indicator enabled |
- A modification of register bit IRQ_POLARITY has no influence to RX_BL_CTRL behavior.
If this register bit is set, the Frame Buffer Empty Indicator is enabled. After sending a Frame Buffer read command, signal IRQ indicates that an access to the Frame Buffer is not possible since PSDU data are not available yet.
The IRQ signal does not indicate any interrupts during this time.
Bits 3:2 – SPI_CMD_MODE[1:0] SPI_CMD_MODE
Each SPI transfer returns bytes back to the SPI master. The content of the first byte (PHY_STATUS) can be configured using register bits SPI_CMD_MODE.
| Value | Description |
|---|---|
| 0x0 | No clock at CLKM, signal set to logic low |
| 0x1 | Monitor TRX_STATUS register |
| 0x2 | Monitor PHY_RSSI register |
| 0x3 | Monitor IRQ_STATUS register |
Bit 1 – IRQ_MASK_MODE IRQ_MASK_MODE
The radio transceiver supports polling of interrupt events. Interrupt polling is enabled by setting register bit IRQ_MASK_MODE.
| Value | Description |
|---|---|
| 0x0 |
Interrupt polling is disabled. Masked off IRQ bits will not appear in IRQ_STATUS register. |
| 0x1 |
Interrupt polling is enabled. Masked off IRQ bits will appear in IRQ_STATUS register. |
With the interrupt polling enabled (IRQ_MASK_MODE = 1) the interrupt events are flagged in the register 0x0F (IRQ_STATUS) when their respective mask bits are disabled in the register 0x0E (IRQ_MASK).
Bit 0 – IRQ_POLARITY IRQ_POLARITY
The register bit IRQ_POLARITY controls the polarity for pin 24 (IRQ). The default polarity of the pin 24 (IRQ) is active high. The polarity can be configured to active low via register bit IRQ_POLARITY.
| Value | Description |
|---|---|
| 0x0 | IRQ signal is high active. |
| 0x1 | IRQ signal is low active. |
- A modification of register bit IRQ_POLARITY has no influence to RX_BL_CTRL behavior.
This setting does not affect the polarity of the Frame Buffer Empty Indicator. The Frame Buffer Empty Indicator is always active high.