14.6.1.7.1 AES_CTRL
The AES_CTRL register controls the operation of the security module.
Note:
- Do not access this register during AES operation to read the AES core status. A read or write access during AES operation stops the actual processing.
- To read the AES status use register bit AES_DONE (register 0x82, AES_STATUS).
| Name: | AES_CTRL |
| Offset: | 0x83 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| AES_REQUEST | AES_MODE[2:0] | AES_DIR | |||||||
| Access | W | R/W | R/W | R/W | R/W | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – AES_REQUEST AES_REQUEST
A write access with AES_REQUEST = 1 initiates the AES operation.
| Value | Description |
|---|---|
| 0x0 | Security module, AES core idle |
| 0x1 | A write access starts the AES operation |
Bits 6:4 – AES_MODE[2:0] AES_MODE
This register bit sets the AES operation mode.
| Value | Description |
|---|---|
| 0x0 | ECB mode |
| 0x1 | KEY mode |
| 0x2 | CBC mode |
| 0x3 - 0x7 | Reserved |
Bit 3 – AES_DIR AES_DIR
The register bit AES_DIR sets the AES operation direction, either encryption or decryption.
| Value | Description |
|---|---|
| 0x0 | AES encryption (ECB, CBC) |
| 0x1 | AES decryption (ECB) |