14.4.8.3 PLL Settling Time and Frequency Agility

When the PLL is enabled during state transition from TRX_OFF to PLL_ON or RX_ON, the settling time is typically t_TR4 = 170µs, including PLL self calibration. A lock of the PLL is indicated with an interrupt IRQ_0 (PLL_LOCK).

Switching between channels within a frequency band in PLL_ON or RX_ON states is typically done within t_{PLL_SW} = 11µs. This makes the radio transceiver highly suitable for frequency hopping applications.

The PLL frequency in PLL_ON and receive states is 1MHz below the PLL frequency in transmit states. When starting the transmit procedure, the PLL frequency is changed to the transmit frequency within a period of t_{RX_TX} = 16µs before really starting the transmission. After the transmission, the PLL settles back to the receive frequency within a period of t_{TX_RX} = 32µs. This frequency step does not generate an interrupt IRQ_0 (PLL_LOCK) or IRQ_1 (PLL_UNLOCK) within these periods.