14.2.1.4.6 State Transition Timing Summary

The AT86RF212B transition numbers correspond to the Basic Operation Mode State Diagram and do not include SPI access time if not otherwise stated. See measurement setup in the Basic Application Schematic.

Table 14-7. State Transition Timing
Symbol	Parameter	Condition	Typ.	Max.	Unit
t_TR1	P_ON⇒CLKM is available	Depends on crystal oscillator setup (Siward A207-011, CL= 10pF) and external capacitor at DVDD (CB3 = 1µF nom.).	420	1000	µs
t_TR1a	SLEEP⇒CLKM is available	Depends on crystal oscillator setup (Siward A207-011, CL= 10pF) and external capacitor at DVDD (CB3 = 1µF nom.).	390	1000	µs
t_TR2	SLEEP⇒TRX_OFF	Depends on crystal oscillator setup (Siward A207-011, CL= 10pF) and external capacitor at DVDD (CB3 = 1µF nom.); TRX_OFF state indicated by IRQ_4 (AWAKE_END).	420	1000	µs
t_TR3	TRX_OFF⇒SLEEP	For f_CLKM> 250kHz.	35		CLKM cycles
t_TR3	TRX_OFF⇒SLEEP	Otherwise.	0		CLKM cycles
t_TR4	TRX_OFF⇒PLL_ON	Depends on external capacitor at AVDD (CB1 = 1µF nom.); The TRX_OFF_AVDD_EN bit in the TRX_CTRL_2 register (TRX_CTRL_2.TRX_OFF_AVDD_EN) is not set.	170		µs
t_TR5	PLL_ON⇒TRX_OFF		1		µs
t_TR6	TRX_OFF⇒RX_ON	Depends on external capacitor at AVDD (CB1 = 1µF nom.); The TRX_OFF_AVDD_EN bit in the TRX_CTRL_2 register (TRX_CTRL_2.TRX_OFF_AVDD_EN) is not set.	170		µs
t_TR7	RX_ON⇒TRX_OFF		1		µs
t_TR8	PLL_ON⇒RX_ON		1		µs
t_TR9	RX_ON⇒PLL_ON	Transition time is also valid for TX_ARET_ON, RX_AACK_ON⇒PLL_ON.	1		µs
t_TR10	PLL_ON⇒BUSY_TX	When asserting pin 11 (SLP_TR) or TRX_CMD = TX_START first symbol transmission is delayed by one symbol period (PLL settling and PA ramp-up).	1		symbol period
t_TR11	BUSY_TX⇒PLL_ON	PLL settling time.	32		µs
t_TR12	Various states⇒TRX_OFF	Using TRX_CMD = FORCE_TRX_OFF (see TRX_STATE.TRX_CMD register bits); not valid for SLEEP⇒TRX_OFF (see t_TR2).	1		µs
t_TR13	RESET⇒TRX_OFF	Not valid for P_ON or SLEEP.	26		µs
t_TR14	Various states⇒PLL_ON	Using TRX_CMD = FORCE_PLL_ON (see TRX_STATE.TRX_CMD register bits); not valid for states SLEEP, P_ON, RESET, TRX_OFF, and *_NOCLK.	1		µs

The state transition timing is calculated based on the timing of the individual blocks shown in the Basic Operating Mode Timing section. The worst case values include maximum operating temperature, minimum supply voltage, and device parameter variations.

Table 14-8. Block Initialization and Settling Time
Symbol	Parameter	Condition	Min.	Typ.	Max.	Unit
t_XTAL	Reference oscillator settling time	Start XTALÞclock available at pin 17 (CLKM). Depends on crystal oscillator setup (Siward A207-011, CL= 10pF).		420	1000	µs
t_FTN	FTN calibration time				25	µs
t_DVREG	DVREG settling time	Depends on external bypass capacitor at DVDD (CB3 = 1µF nom., 10µF worst case).		150	1500	µs
t_AVREG	AVREG settling time	Depends on external bypass capacitor at AVDD (CB1 = 1µF nom., 10µF worst case).		150	1500	µs
t_{PLL_INIT}	Initial PLL settling time	PLL settling time TRX_OFF⇒PLL_ON, including 150µs AVREG settling time.		170	370	µs
t_{PLL_SW}	PLL settling time on channel switch	Duration of channel switch within frequency band.		11	42	µs
t_{PLL_CF}	PLL CF calibration	PLL center frequency calibration.	8	8	270	µs
t_{PLL_DCU}	PLL DCU calibration	PLL DCU calibration.		10	10	µs
t_{RX_TX}	RX⇒TX	Maximum settling time RX⇒TX.			16	µs
t_{TX_RX}	TX⇒RX	Maximum settling time TX⇒RX.			32	µs
t_RSSI	RSSI, update	RSSI update period in receive states.
		BPSK-20:		32		µs
		BPSK-40:		24		µs
		O-QPSK:		8		µs
t_ED	ED measurement	ED measurement period is eight symbols. Different timing within High Data Rate Modes.		8		symbol
t_CCA	CCA measurement	CCA measurement period is eight symbols.		8		symbol
t_RND	Random value, update	Random value update period.		1		µs
t_AES	AES core cycle time			23.4	24	µs