14.1.7.2 Interrupt Mask Modes and Pin Polarity

If the IRQ_MASK_MODE bits in the TRX_CTRL_1 register (TRX_CTRL_1.IRQ_MASK_MODE) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked. However, in that case no timing information for this interrupt is provided.

Table 14-6. IRQ Mask Configuration
IRQ_MASK ValueIRQ_MASK_MODEDescription
00IRQ is suppressed entirely and none of interrupt sources are shown in register IRQ_STATUS.
01IRQ is suppressed entirely but all interrupt causes are shown in register IRQ_STATUS.
≠ 00All enabled interrupts are signaled on IRQ pin and are also shown in register IRQ_STATUS.
≠ 01All enabled interrupts are signaled on IRQ pin and all interrupt causes are shown in register IRQ_STATUS.
Figure 14-17. IRQ_MASK_MODE = 0
Figure 14-18. IRQ_MASK_MODE = 1

The AT86RF212B IRQ pin polarity can be configured with the IRQ_POLARITY bit in the TRX_CTRL_1 register (TRX_CTRL_1.IRQ_POLARITY). The default behavior is active high, which means that pin 24 (IRQ) = H issues an interrupt request.

If the “Frame Buffer Empty Indicator” is enabled during Frame Buffer read access, the IRQ pin has an alternative functionality.

A solution to monitor the IRQ_STATUS register (without clearing it) is described in Section BBD.