14.8.15 IRQ_STATUS
The IRQ_STATUS register contains the status of the pending interrupt requests.
By reading the register after an interrupt is signaled by the IRQ signal to the
microcontroller the source of the issued interrupt can be identified. A read access
to this register resets all interrupt bits, and so clears the IRQ_STATUS register.
Note:
- If the IRQ_MASK_MODE bit in the TRX_CTRL_1 register is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked; refer to Figure 14-18. However in that case no timing information for this interrupt is provided.
- If the IRQ_MASK_MODE bit in the TRX_CTRL_1 is set, it is recommended to read the interrupt status register (IRQ_STATUS) first to clear the history.
| Name: | IRQ_STATUS |
| Offset: | 0x0F |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IRQ_7_BAT_ LOW | IRQ_6_TRX_ UR | IRQ_5_AMI | IRQ_4_ CCA_ED_ DONE | IRQ_3_TRX_ END | IRQ_2_RX_ START | IRQ_1_PLL_ UNLOCK | IRQ_0_PLL_ LOCK | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – IRQ_7_BAT_ LOW IRQ_7_BAT_ LOW
Bit 6 – IRQ_6_TRX_ UR IRQ_6_TRX_ UR
Bit 5 – IRQ_5_AMI IRQ_5_AMI
Bit 4 – IRQ_4_ CCA_ED_ DONE IRQ_4_ CCA_ED_ DONE
Multi-functional interrupt:
- AWAKE_END: Indicates finished transition to TRX_OFF state from P_ON, SLEEP, DEEP_SLEEP, or RESET state.
- CCA_ED_DONE: Indicates the end of a CCA or ED measurement.
Bit 3 – IRQ_3_TRX_ END IRQ_3_TRX_ END
RX: Indicates the completion of a frame reception.
TX: Indicates the completion of a frame transmission.
Bit 2 – IRQ_2_RX_ START IRQ_2_RX_ START
Indicates the start of a PSDU reception; the AT86RF233 state changed to BUSY_RX; the PHR can be read from Frame Buffer.
Bit 1 – IRQ_1_PLL_ UNLOCK IRQ_1_PLL_ UNLOCK
Indicates PLL unlock. If the radio transceiver is in BUSY_TX / BUSY_TX_ARET state, the PA is turned off immediately.