14.1.7.1 Overview

The AT86RF212B differentiates between nine interrupt events (eight physical interrupt registers, one shared by two functions). Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each pending interrupt is flagged in the interrupt status register. All interrupt events are OR-combined to a single external interrupt signal (IRQ pin). If an interrupt is issued pin 24 (IRQ) = H, the microcontroller shall read the interrupt status register 0x0F (IRQ_STATUS) to determine the source of the interrupt. A read access to this register clears the interrupt status register and thus the IRQ pin, too.

Interrupts are not cleared automatically when the event trigger for respective interrupt flag bit in the register 0x0F (IRQ_STATUS) is no longer active. Only a read access to register 0x0F (IRQ_STATUS) clears the flag bits. Exceptions are IRQ_0 (PLL_LOCK) and IRQ_1 (PLL_UNLOCK) where each is cleared in addition by the appearance of the other.

The supported interrupts for the Basic Operating Mode are summarized in table below.

Table 14-5. Interrupt Description in Basic Operating Mode
IRQ Name Description
IRQ_7 (BAT_LOW) Indicates a supply voltage below the programmed threshold.
IRQ_6 (TRX_UR) Indicates a Frame Buffer access violation.
IRQ_5 (AMI) Indicates address matching.
IRQ_4 (CCA_ED_DONE)

Multi-functional interrupt:

1. AWAKE_END:

  • Indicates radio transceiver reached TRX_OFF state at the end of P_ON ⇨ TRX_OFF and SLEEP ⇨ TRX_OFF state transition.

2. CCA_ED_DONE:

  • Indicates the end of a CCA or ED measurement.
IRQ_3 (TRX_END)

RX: Indicates the completion of a frame reception.

TX: Indicates the completion of a frame transmission.
IRQ_2 (RX_START)

Indicates the start of a PSDU reception; the AT86RF212B state changed to BUSY_RX;

the PHR can be read from Frame Buffer.
IRQ_1 (PLL_UNLOCK) Indicates PLL unlock. If the radio transceiver is in BUSY_TX / BUSY_TX_ARET state, the PA is turned off immediately.
IRQ_0 (PLL_LOCK) Indicates PLL lock.
Note: The IRQ_4 (AWAKE_END) interrupt can usually not be seen when the transceiver enters TRX_OFF state after P_ON or RESET, because register 0x0E (IRQ_MASK) is reset to mask all interrupts. It is recommended to enable IRQ_4 (AWAKE_END) to be notified once the TRX_OFF state is entered.