14.4.7.4 Master Clock Signal Output (CLKM)

The generated reference clock signal can be fed into a microcontroller using pin 17 (CLKM). The internal 16MHz raw clock can be divided by an internal prescaler. Thus, clock frequencies of 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 250kHz, or the current SHR symbol rate frequency can be supplied by pin 17 (CLKM).

The CLKM frequency update scheme and pin driver strength is configurable using the TRX_CTRL_0 register. There are two possibilities how a CLKM frequency change gets effective:

If CLKM_SHA_SEL = 0 and/or CLKM_CTRL = 0, changing the CLKM_CTRL bits in the TRX_CTRL_0 register (TRX_CTRL_0.CLKM_CTRL) will immediately affects a glitch free CLKM clock rate change.

Otherwise (CLKM_SHA_SEL = 1 and CLKM_CTRL > 0 before changing the CLKM_CTRL bits), the new clock rate is supplied when leaving the SLEEP state the next time.

To reduce power consumption and spurious emissions, it is recommended to turn off the CLKM clock when not in use or to reduce its driver strength to a minimum.

Note:

During reset procedure the CLKM_CTRL bits are shadowed. Although the clock setting of CLKM remains after reset, a read access to register bits CLKM_CTRL delivers the reset value one. For that reason, it is recommended to write the previous configuration (before reset) to register bits CLKM_CTRL (after reset) to align the radio transceiver behavior and register configuration. Otherwise, the CLKM clock rate is set back to the reset value (1MHz) after the next SLEEP cycle.

For example, if the CLKM clock rate is configured to 16MHz, the CLKM clock rate remains at 16MHz after a reset, however, the register bits CLKM_CTRL are set back to one. Since CLKM_SHA_SEL reset value is one, the CLKM clock rate changes to 1MHz after the next SLEEP cycle if the CLKM_CTRL setting is not updated.