14.8.3 TRX_CTRL_0
| Name: | TRX_CTRL_0 |
| Offset: | 0x03 |
| Reset: | 0x19 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PAD_IO[1:0] | PAD_IO_CLKM[1:0] | CLKM_SHA_SEL | CLKM_CTRL[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 1 | 1 | 0 | 1 | ||
Bits 7:6 – PAD_IO[1:0] PAD_IO
These register bits set the output driver current of digital output pads, except CLKM.
| Value | Description |
|---|---|
| 0x0 | 2mA |
| 0x1 | 4mA |
| 0x2 | 6mA |
| 0x3 | 8mA |
- Selecting low-level driver current reduces power consumption and minimizes transceiver’s harmonic distorion.
Bits 5:4 – PAD_IO_CLKM[1:0] PAD_IO_CLKM
These register bits set the output driver current of pin CLKM. It is recommended to reduce the driver strength to 2mA (PAD_IO_CLKM = 0) if possible. This reduces power consumption and spurious emissions.
| Value | Description |
|---|---|
| 0x0 | 2mA |
| 0x1 | 4mA |
| 0x2 | 6mA |
| 0x3 | 8mA |
Bit 3 – CLKM_SHA_SEL CLKM_SHA_SEL
The register bit CLKM_SHA_SEL defines whether a new clock rate (defined by CLKM_CTRL) is set immediately or gets effective after the next SLEEP cycle.
| Value | Description |
|---|---|
| 0x0 | CLKM clock rate change appears immediately |
| 0x1 | CLKM clock rate change appears after SLEEP cycle |
Bits 1:0 – CLKM_CTRL[1:0] CLKM_CTRL
The register bits CLKM_CTRL set the clock rate of CLKM.
| Value | Description |
|---|---|
| 0x0 | No clock at CLKM, signal set to logic low |
| 0x1 | 1MHz |
| 0x2 | 2MHz |
| 0x3 | 4MHz |
| 0x4 | 8MHz |
| 0x5 | 16MHz |
| 0x6 | 250kHz |
| 0x7 | 62.5kHz (IEEE 802.15.4 symbol rate) |
- If a clock rate is selected between 1MHz and 16MHz and SLP_TR is set to logic high in state TRX_OFF, the TRX delivers additional 35 clock cycles before entering state SLEEP.