14.2.2.3.1 Description of RX_AACK Configuration Bits
RX_AACK configuration as described below shall be done prior to switching the AT86RF212B into state RX_AACK_ON.
The table below summarizes all register bits which affect the behavior of an RX_AACK transaction. For frame filtering it is further required to setup address registers to match the expected address.
| Register Address | Register Bits | Register Name | Description |
|---|---|---|---|
|
0x20,0x21 0x22,0x23 0x24 … 0x2B |
SHORT_ADDR_0/1 PAN_ADDR_0/1 IEEE_ADDR_0 … IEEE_ADDR_7 | Setup Frame Filter. | |
| 0x0C | 7 | RX_SAFE_MODE | Dynamic frame buffer protection. |
| 0x17 | 1 | AACK_PROM_MODE | Support promiscuous mode. |
| 0x17 | 2 | AACK_ACK_TIME | Change auto acknowledge start time. |
| 0x17 | 4 | AACK_UPLD_RES_FT | Enable reserved frame type reception, needed to receive non-standard compliant frames. |
| 0x17 | 5 | AACK_FLTR_RES_FT | Filter reserved frame types like data frame type, needed for filtering of non-standard compliant frames. |
| 0x2C | 0 | SLOTTED_OPERATION | If set, acknowledgment transmission has to be triggered by pin 11 (SLP_TR). |
| 0x2E | 3 | AACK_I_AM_COORD | If set, the device is a PAN coordinator, that is responds to a null address. |
| 0x2E | 4 | AACK_DIS_ACK | Disable generation of acknowledgment. |
| 0x2E | 5 | AACK_SET_PD | Set frame pending subfield in Frame Control Field (FCF). |
| 0x2E | 7:6 | AACK_FVN_MODE | Controls the ACK behavior, depending on FCF frame version number. |
The usage of the RX_AACK configuration bits for various operating modes of a node is explained in the following sections. Configuration bits not mentioned in the following two sections should be set to their reset values.
The general behavior of the AT86RF212B Extended Feature Set settings:
- SFD_VALUE (alternative SFD value)
- ANT_DIV (Antenna Diversity)
- RX_PDT_LEVEL (blocking frame reception of lower power signals)
are completely independent from RX_AACK mode and can be arbitrarily combined.