44.7.3 I2SMCC Mode Register B

This register can only be written if WPCFEN is cleared in the Inter-IC Sound Write Protection Mode Register.

The I2SMCC_MRB must only be written when the I2SMCC is stopped in order to avoid unexpected behavior on the I2SMCC_WS, I2SMCC_CK and I2SMCC_DOUT outputs. The proper sequence is to write to I2SMCC_MRB, then write to I2SMCC_CR to enable the I2SMCC or to disable the I2SMCC before writing a new value to I2SMCC_MRB.

Name: I2SMCC_MRB
Offset: 0x08
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
       DMACHUNK[1:0] 
Access R/WR/W 
Reset 00 
Bit 76543210 
          
Access  
Reset  

Bits 9:8 – DMACHUNK[1:0] DMA Chunk Size

ValueNameDescription
0 1_WORD A DMA transfer request is issued when at least 1 word is empty in the FIFO.
1 2_WORDS A DMA transfer request is issued when at least 2 words are empty in the FIFO.
2 4_WORDS A DMA transfer request is issued when at least 4 words are empty in the FIFO.

Limitations exist when operating in Mono or TDM. See TX DMA Chunk Configurations and RX DMA Chunk Configurations.

3 8_WORDS A DMA transfer request is issued when at least 8 words are empty in the FIFO.

Limitations exist when operating in Mono or TDM. See TX DMA Chunk Configurations and RX DMA Chunk Configurations.