44.7.1 I2SMCC Control Register
This register can only be written if WPCTEN is cleared in the Inter-IC Sound Write Protection Mode Register.
| Name: | I2SMCC_CR |
| Offset: | 0x00 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWRST | TXDIS | TXEN | CKDIS | CKEN | RXDIS | RXEN | |||
| Access | W | W | W | W | W | W | W | ||
| Reset | – | – | – | – | – | – | – |
Bit 7 – SWRST Software Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Resets all the registers in the I2SMCC. The I2SMCC is disabled after the reset. |
Bit 5 – TXDIS Transmitter Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the I2SMCC transmitter. I2SMCC_SR.TXEN is cleared when the Transmitter is stopped. |
Bit 4 – TXEN Transmitter Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the I2SMCC transmitter, if TXDIS is not ‘1’. I2SMCC_SR.TXEN is set when the Transmitter is started. |
Bit 3 – CKDIS Clocks Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the I2SMCC clock generation. |
Bit 2 – CKEN Clocks Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the I2SMCC clock generation, if CKDIS is not ‘1’. |
Bit 1 – RXDIS Receiver Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the I2SMCC receiver. I2SMCC_SR.RXEN is cleared when the receiver is stopped. |
Bit 0 – RXEN Receiver Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the I2SMCC receiver, if RXDIS is not ‘1’. I2SMCC_SR.RXEN is set when the receiver is activated. |