44.7.4 I2SMCC Status Register

Name: I2SMCC_SR
Offset: 0x0C
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
    TXEN   RXEN 
Access RR 
Reset 00 

Bit 4 – TXEN Transmitter Enabled

TXEN=1 if the selected clock (internal bit clock, see the figure I2SMCC Clock Generation) is active and WS is active.
ValueDescription
0

Cleared when the transmitter is disabled, following a I2SMCC_CR.TXDIS or I2SMCC_CR.SWRST request.
1

Set when the transmitter is enabled, following a I2SMCC_CR.TXEN request.

Bit 0 – RXEN Receiver Enabled

RXEN=1 if the selected clock (internal bit clock, see the figure I2SMCC Clock Generation) is active and WS is active.
ValueDescription
0

Cleared when the receiver is disabled, following an RXDIS or SWRST request in I2SMCC_CR.
1

Set when the receiver is enabled, following an RXEN request in I2SMCC_CR.