40.4.12 Wake-on-LAN Support

The receive block supports Wake-on-LAN by detecting the following events on incoming receive frames:

  • Magic packet
  • ARP request to the device IP address
  • Specific address 1 filter match
  • Multicast hash filter match

If one of these events occurs Wake-on-LAN detection is indicated by asserting the wol output pin for 64 rx_clk cycles. These events can be individually enabled through bits 19:16 of the Wake-on-LAN Register (EMAC_WOL). Also, for Wake-on-LAN detection to occur, receive enable must be set in the EMAC_NCR, however a receive buffer does not have to be available. wol assertion due to ARP request, specific address 1 or multicast filter events occurs even if the frame is errored. For magic packet events, the frame must be correctly formed and error free.

A magic packet event is detected if all of the following are true:

  • magic packet events are enabled through bit 16 of the EMAC_WOL register
  • the frame’s destination address matches specific address 1
  • the frame is correctly formed with no errors
  • the frame contains at least 6 bytes of 0xFF for synchronization
  • there are 16 repetitions of the contents of specific address 1 register immediately following the synchronization

An ARP request event is detected if all of the following are true:

  • ARP request events are enabled through bit 17 of the EMAC_WOL register
  • broadcasts are allowed by bit 5 in the EMAC_NCFGR
  • the frame has a broadcast destination address (bytes 1 to 6)
  • the frame has a type ID field of 0x0806 (bytes 13 and 14)
  • the frame has an ARP operation field of 0x0001 (bytes 21 and 22)
  • the least significant 16 bits of the frame’s ARP target protocol address (bytes 41 and 42) match the value programmed in bits 15:0 of the EMAC_WOL register

The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame. The reserved value of 0x0000 for the Wake-on-LAN target address value does not cause an ARP request event, even if matched by the frame.

A specific address 1 filter match event occurs if all of the following are true:

  • specific address 1 events are enabled through bit 18 of the EMAC_WOL register
  • the frame’s destination address matches the value programmed in the specific address 1 registers

A multicast filter match event occurs if all of the following are true:

  • multicast hash events are enabled through bit 19 of the EMAC_WOL register
  • multicast hash filtering is enabled through bit 6 of the EMAC_NCFGR
  • the frame’s destination address matches against the multicast hash filter
  • the frame’s destination address is not a broadcast