40.4.13 PHY Maintenance
The PHY Maintenance Register (EMAC_MAN) enables the EMAC to communicate with a PHY by means of the MDIO interface. It is used during auto-negotiation to ensure that the EMAC and the PHY are configured for the same speed and duplex configuration.
The EMAC_MAN register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit 2 is set in the Network Status Register (EMAC_NSR) (about 2000 MCK cycles later when bit 10 is set to zero, and bit 11 is set to one in the EMAC_NCFGR). An interrupt is generated as this bit is set. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO.
Reading during the shift operation returns the current contents of the shift register. At the end of management operation, the bits have shifted back to their original locations. For a read operation, the data bits are updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bits 31:28 should be written as 0x0011. To write clause 45 PHYs, bits 31:28 should be written as 0x0001. See the table below.
| PHY | Access | Field Configuration (EMAC_MAN Bits 31:28) | |
|---|---|---|---|
| SOF[1:0] | RW[1:0] | ||
| Clause 22 | Read | 01 | 10 |
| Write | 01 | 01 | |
| Clause 45 | Read | 00 | 11 |
| Write | 00 | 01 | |
| Read + Address | 00 | 10 | |
For a description of MDC generation, see Network Configuration Register.