40.4.14 Physical Interface
Depending on products, the Ethernet MAC is capable of interfacing to RMII or MII Interface. The ‘RMII’ bit in the User Input/Output Register (EMAC_USRIO) controls the interface that is selected. When this bit is set, the RMII interface is selected, else the MII interface is selected.
The MII and RMII interfaces are capable of both 10 Mbit/s and 100 Mbit/s data rates as described in the IEEE 802.3u standard. The signals used by the MII and RMII interfaces are described in the table below.
| Pin Name | MII | RMII |
|---|---|---|
| ETXCK_EREFCK | ETXCK: Transmit Clock | EREFCK: Reference Clock |
| ECRS | ECRS: Carrier Sense | – |
| ECOL | ECOL: Collision Detect | – |
| ERXDV | ERXDV: Data Valid | ECRSDV: Carrier Sense/Data Valid |
| ERX0–ERX3 | ERX0–ERX3: 4-bit Receive Data | ERX0–ERX1: 2-bit Receive Data |
| ERXER | ERXER: Receive Error | ERXER: Receive Error |
| ERXCK | ERXCK: Receive Clock | – |
| ETXEN | ETXEN: Transmit Enable | ETXEN: Transmit Enable |
| ETX0–ETX3 | ETX0–ETX3: 4-bit Transmit Data | ETX0–ETX1: 2-bit Transmit Data |
| ETXER | ETXER: Transmit Error | – |
| EMDC | Management Data Clock | Management Data Clock |
| EMDIO | Management Data Input Output | Management Data Input Output |
The RMII provides a reduced pin count alternative to the IEEE 802.3u MII. It uses two bits for transmit (ETX0 and ETX1) and two bits for receive (ERX0 and ERX1). There is a Transmit Enable (ETXEN), a Receive Error (ERXER), a Carrier Sense (ECRS_DV), and a 50 MHz Reference Clock (ETXCK_EREFCK) for 100 Mbit/s data rate.